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Description
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
THE ROLE:
Package design and SI/PI and PDN topology assessment for advanced packages in AMD AECG package design and development team. Serdes PKG design extraction and tuning for next gen links. Simulate die and package electrical performance from design and forward-looking technologies -including silicon/TSV, package stack-up/routing/PDN and discrete decoupling capacitors evaluation. Utilize techniques in model generation, simulation, and validation and EM (Electromagnetic) for correlating hardware measurements versus pre/post-layout simulation. Drive cost reduction through the adoption of leading-edge package technology while achieving performance-driven objectives.
THE PERSON:
The ideal candidate will be part of package integration team working with layout, electrical and silicon design teams to assess product package definition, system performance and cost tradeoff, technology design rule development and package structure planning. Team player and able to contribute individually.
KEY RESPONSIBILITIES:
- Package SI/PI architect responsible to demonstrate package electrical performance
- HFSS extraction of PKG and tuning for target specs.
- Extract Die grid model and/or integrate models into system level PDN sims.
- Simulation and validation for correlating hardware measurements versus pre/post-layout simulation, effecting signal integrity-driven design flow for advanced FPGA & Adaptive SOC product development
- Drive cost reduction through the adoption of leading-edge package technology while achieving performance-driven objectives
PREFERRED EXPERIENCE:
- Solid background in fundamentals of SI, PI, circuit, and transmission-line theory.
- Familiar with some of these tools - Cadence PowerDC, PowerSI, Ansys HFSS & Redhawk, Keysight ADS, Siemens Hyperlynx, Cadence Allegro, Ansys Q3D, Synopsys Hspice
- Possesses an understanding of high-speed serdes, memory interface, supply voltage noise, and packaging technologies/trends to drive package design validation throughout all phases of the product cycle
- Understand in-depth package development flow and work fluently with NPI process to synthesize a cohesive package introduction plan
- Interface and negotiate effectively across engineering teams to balance performance adequacy and schedule commitment
- Drive package design review, manage modeling/simulation projects, prepare and present the final design review (FDR) to all product partners
- Collaborate with silicon IP and package technology teams to establish the development plan and timeline for the R&D project, test vehicle, and prototype packages
- Industry experience in IC package technology and product development in the semiconductor industry with consistent track record
- Demonstrate technical leadership in complex product development under challenging technical and schedule conditions
ACADEMIC CREDENTIALS:
BS, MS or higher in Electrical Engineering or Computer Engineering or related field.
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Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
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