Description
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
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AMD has an opening for a Staff Automotive Functional Safety Engineer in the SOC Functional Safety team. This team is responsible for ensuring compliance to Automotive Functional Safety standard ISO26262 for existing and future generations of the Adaptable Compute Acceleration Platform (ACAP).
KEY RESPONSIBILITIES:
In this onsite/hybrid role, you will contribute across the following diverse set of activities leading to the certification of our ACAP for usage in automotive applications:
- Requirements management and traceability
- Review of Safety Concept
- Specification of Microarchitecture and creation of reusable RTL components for FuSa library
- Safety Analyses such as DFMEA, DFA and FMEDA on designs that utilize latest technologies from market leaders in ASIC/SOC IP such as Arm as well as internally developed IP
- Guidance and review of verification, fault injection and validation efforts across block level verif/val teams
- Preparation of work products for ISO26262 and IEC61508 assessments
Required Qualifications:
- MSEE with 10 years of experience or equivalent
- Experience with ISO26262 specific safety analyses and work products (FMEA, FMEDA, DFA)
- Experience in designing or analyzing RTL blocks for an SOC, ASIC or FPGA
- Understanding of safety mechanisms such as Parity, ECC, CRC, Watchdog timer, Voltage/temperature monitoring
- Execution of quality checks to improve quality of RTL/UPF/SDC deliverables
- Analysis of design metrics and making implementation choices to optimize PPA
- Targeting SOC RTL to process technology
- Facilitating DFx/MBIST instrumentation
- Basic understanding of synthesis and place&route processes in SOC/ASIC or FPGA design context
- Understanding of testbenches for verification of RTL designs
- Experience or understanding of fault injection simulations and fault grading
- Simulation and debugging experience using VCS, IES, Verdi or similar
- Experience with silicon validation of processor based designs
- Experience in building automation using scripting languages as PERL, Python or TCL
- Ability to lead others, junior engineers or cross functional teams, through safety analyses
Desired Qualifications:
TCL and Python scripting
Understanding of verification using UVM and pre-silicon validation using prototyping platforms- Understanding of ARM architecture and APB, AXI, ACE, CHI protocols and network on chip blocks
- Understanding of common analog blocks such as PLL, ADC, SerDes
- Understanding of multiple power domains
- Experience working in design teams distributed over multiple sites
- Post-silicon validation and debug experience
- FPGA knowledge and emulation experience
- Fluent in working with Linux environment and version control systems such as Git or Perforce
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
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Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
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